Design Flow is very important for standard libarary based ASIC design, below is the tentative flow for our multiple processor chip

  

     Flow                    Tool                 Tasks 

   Synthesis                     Design_compiler        synthesis script,special modules(Oscillator,MAC, Memory, Configure)
       |        
   Dynamic-Sim after synth       NCverilog              make sure all available tests work
       |
   layout for single processor   Encounter              script (design input,floorplan,placement,clock tree,route)
       |                                                bypass capacitor insertion
       |
   Extract processor data        Encounter              RC Extraction for delay analysis
       |
   In-place optimization         Encounter?             make small changes to improve timing
       |
   Dynamic-sim after layout      NCVerilog and Hspice   make sure testbench works
   DRC, LVS                      icfb diva              pass the DRC and LVS
   static timing analysis        Primetime              meeting the static timing
       |
   layout for chip               Encounter/icfb         Placement of PAD and each processor
       |
   Extract chip data
       |
   Dynamic-Sim after layout      NCVerilog and Hspice   make sure testbench works
   DRC, LVS                      icfb diva              pass the DRC and LVS
   static_analysis               Primetime              meeting the static timing


  Major physical blocks
  ==================================
  Processor
  Big memory
  Config controller 
  I/O pads

  Open Issues and Things to Remember
  ==================================
  Clock oscillator
    - possible to power with its own clean supply and ground?
    - place many bypass capacitors around it

  Tying off processor ports
    - 12-bit processor addresses
    - unused NSEW port(s) on edge processors
    - unused big memory ports
    - use TIEHI and TIELO cells? (safer)  or wire off by hand? (easy)
    - may be best to wrap processor tile in another module

  Integrating memory macros into the flow
    - are we confident it will work?
    - consider two processor types: one with all flip-flops