[VLSI Computation Lab]

Asynchronous Array of Simple Processors (AsAP) project pre-tapeout "Checklist"

 o Oscillator
 o Glue block
     - SPI interface (Jeremy)
     - global clk-out muxing. How do we do this? 1) use SPI command to select
       2) each processor outputs a config bit for this but only one column's 
       gets used?)
 o Power
     - pads
     - grid
     - separate power for oscillators?
     - bypass capacitors?
 o Test
     - debug bus
          - PC
          - stall input
          - stall output
          - stall NOP
          - FIFO state (empty, full, wr_request, wr clock, etc.
          - No: source1, source2, result  (can test with software)
          - others?  how wide is the bus?  how do we group them?
     - probe pads
     - scan path? (probably not)
 o Add processor ports for "pass through" signals  (Eric)
     - debug bus
 o Test: software FIFO (can we peek the FIFO?)
 o Run tests at different clock frequencies and reserve space

 o Task related to the place & route design for a single processor
   1. Load design information, 
      include Verilog, LEF, Timing Lib, Timing constrains, Power name
   2. Floorplan
      2.1 Specify Floorplan, include unitization, distance to side ..
      2.2 Specify Pin Position
      2.3 Place the memory macro: 
          position, black halo, routing blockage, etc.
      2.4 Power Planning
          use Mt2 and Mt1 to supply the standard cell, 
          use Mt6 and Mt5 to supply M2 and M1 in each 80um*80um block
   3. Placement
   4. Clock tree design
   5. Place FILLER
   6. Route
      6.1 Route for Power
      6.2 Route for cell
   7. Verify in Encounter
      7.1 Verify Connectivity: Open, unconnect, antenna
      7.2 Vefify Geometry, similar as DRC
      7.3 Verify timing, include setup time, holdtime
   8. DRC, LVS in another tool such as icfb, dracular (optiomal)
   9. Static timimg check in another tool such as Primetime (optimal)
   10. Spice simulation (if schemetic viewer available)
 o Final checks before tapeout
    - Verify no latches in gate netlist
    - Verify no tri-state gates in gate netlist
    - Verify no extra false paths in synthesis scripts
    - Gate netlist simulations (with final final netlist)
       - test bus

VCL | ECE Dept. | UC Davis

Last update: April 4, 2005