An Energy-Efficient Single-Chip FFT Processor

Bevan M. Baas
Department of Electrical Engineering
Stanford University
Stanford, CA

Abstract:

A 1024-point single-chip Fast Fourier Transform processor that employs algorithm, architecture, and circuit techniques to achieve an energy efficiency over 60x greater than the best known published processor, is presented. It is designed to operate at supply voltages less than 400mV in a low threshold-voltage CMOS technology, and uses a unique "data-caching" memory architecture and "hierarchical bitline" memories to reduce power.

Paper

Reference

Bevan M. Baas, An Energy-Efficient Single-Chip FFT Processor, IEEE Symposium on VLSI Circuits, May 1996.

BibTeX Entry

@inproceedings{baas:vlsi:1996,
   author    = {Bevan M. Baas},
   title     = {An Energy-Efficient Single-Chip {FFT} Processor},
   booktitle = "IEEE Symposium on {VLSI} Circuits",
   year      = 1996,
   month     = jun,
   pages     = {164--165}
   }
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