An architecture that is well matched to DSP system workloads, enables high-throughput and high energy-efficiency, and is well suited for advancing VLSI fabrication technologies is presented. These processing systems consist of large numbers of simple uniform programmable processing elements communicating asynchronously through a configurable 2-D mesh network that connects adjacent processors at full clock rates. Early estimates predict an area density of 0.15 mm^2 per processor in 0.13 um CMOS. Results from mapping a 16-tap FIR filter over 85 design configurations show a factor of 9 variation in throughput per processor and validate the efficiency of the proposed processor granularity.
Bevan M. Baas. "A Parallel Programmable Energy-Efficient Architecture For Computationally-Intensive DSP Systems." In Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, November 2003.
@inproceedings{Baas:2003:PPE,
author = {Bevan M. Baas},
title = {A Parallel Programmable Energy-Efficient Architecture
For Computationally-Intensive {DSP} Systems},
booktitle = {Signals, Systems and Computers, 2003. Conference Record of
the Thirty-Seventh Asilomar Conference on},
year = 2003,
month = nov
}
Last update: March 15, 2004