A Generalized Cached-FFT Algorithm

Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


Fast Fourier Transform (FFT) algorithms are typically designed to minimize the number of multiplications and additions while maintaining a simple form. Few FFT algorithms are designed to take advantage of hierarchical memory systems, which are easy to include in special-purpose processors, and nearly universal in modern programmable processors. We present a new generalized algorithm, called the cached-FFT, which is designed explicitly to operate on a processor with a hierarchical memory system. By taking advantage of a small and fast cache memory, the algorithm enables higher clock frequencies (for special-purpose processor applications), reduced data communication energy, and increased energy-efficiency—since smaller memories require lower energy per access and can be positioned closer to the processor.



Bevan M. Baas, "A Generalized Cached-FFT Algorithm", In Proceedings of The IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), March 2005, pp. V-89-92.

BibTeX entry

   author    = {Bevan M. Baas},
   title     = {A Generalized {Cached-FFT} Algorithm},
   booktitle = {IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'07)},
   year      = 2005,
   month     = mar,
   pages     = {V-89-92}

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