An Asynchronous Array of Simple Processors for DSP Applications

Zhiyi Yu
Michael Meeuwsen
Ryan Apperson
Omar Sattari
Michael Lai
Jeremy Webb
Eric Work
Tinoosh Mohsenin
Mandeep Singh
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


An array of simple programmable processors designed for DSP applications is implemented in 0.18 µm CMOS and contains 36 asynchronously clocked independent processors. The processors operate at 475 MHz; and each processor dissipates 32 mW while executing applications, 84 mW while 100% active, and 144 mW worst-case at 1.8 V. Each processor occupies 0.66 mm2.


Presentation Slides


Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas. "An Asynchronous Array of Simple Processors for DSP Applications." In Proceedings of the IEEE International Solid-State Circuits Conference, (ISSCC '06) , February 2006, pp.428-429.

BibTeX entry

   author    = {Zhiyi Yu and Michael Meeuwsen and Ryan Apperson and 
               Omar Sattari and Michael Lai and Jeremy Webb and 
               Eric Work and Tinoosh Mohsenin and Mandeep Singh and 
               Bevan M. Baas},
   title     = {An Asynchronous Array of Simple Processors for DSP Applications},
   booktitle = {IEEE International Solid-State Circuits Conference, (ISSCC '06)},
   month     = feb,
   year      = 2006,
   pages     = {428-429}

VCL Lab | ECE Dept. | UC Davis

Last update: February 10, 2006