Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors

Bevan Baas
Zhiyi Yu
Michael Meeuwsen
Omar Sattari
Ryan Apperson
Eric Work
Jeremy Webb
Michael Lai
Daniel Gurman
Chi Chen
Jason Cheung
Dean Truong
Tinoosh Mohsenin
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


The Asynchronous Array of simple Processors (AsAP) comprises
a 2-D array of 16-bit fixed-point programmable processors
with small memories interconnected by a reconfigurable mesh
network.  Processors are well suited for implementation
in future fabrication technologies, and are clocked in a
Globally Asynchronous Locally Synchronous (GALS) fashion.
Individual oscillators fully halt (leakage only) in 9 cycles
when there is no work to do, and restart at full speed in less
than one cycle after work is available.

The multi-processor architecture efficiently makes use of task-level parallelism in many complex DSP applications, and also efficiently computes many large tasks utilizing fine-grain parallelism.

A chip containing 36 (6x6) programmable processors was fabricated in 0.18 µm CMOS using standard cells and is fully functional. The chip operates at 475 MHz at 1.8 V and each processor dissipates 32 mW on average while executing applications. At 0.9 V, the average application power is 2.4 mW at 116 MHz. Each processor occupies only 0.66 mm2.

The architecture enables a clean separation between programming and inter-processor timing handled entirely by hardware. A recently completed C compiler further simplifies programming.

Many DSP and general tasks have been coded including 32-1024 point FFTs, a k=7 viterbi decoder, a JPEG encoder, and a complete IEEE 802.11g/11a wireless LAN baseband transmitter. Power, throughput, and area results compare very well with existing programmable DSP processors.

Presentation Slides

Official HotChips online copies


Bevan Baas, Zhiyi Yu, Michael Meeuwsen, Omar Sattari, Ryan Apperson, Eric Work, Jeremy Webb, Michael Lai, Daniel Gurman, Chi Chen, Jason Cheung, Dean Truong, Tinoosh Mohsenin. "Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors." In Proceedings of the IEEE HotChips Symposium on High-Performance Chips (HotChips 2006), August 2006.

BibTeX Entry

   author    = {Bevan Baas and Zhiyi Yu and Michael Meeuwsen 
               and Omar Sattari and Ryan Apperson and Eric Work 
               and Jeremy Webb and Michael Lai and Daniel Gurman 
	       and Chi Chen and Jason Cheung 
               and Dean Truong and Tinoosh Mohsenin},
   title     = {Hardware and Applications of {AsAP}: An Asynchronous Array
               of Simple Processors},
   booktitle = {IEEE HotChips Symposium on High-Performance Chips
               (HotChips 2006)},
   month     = {Aug.},
   year      = {2006}

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Last update: Feb. 1, 2011