Split-row: A reduced complexity, high throughput LDPC decoder architecture

Tinoosh Mohsenin
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors which results in smaller area, higher speeds, and lower energy dissipation. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with Split-Row decoding is within 0.3-0.6 dB of the Min-Sum and Sum-Product decoding algorithms. A full parallel decoder for a (3,6) LDPC code with a code length of 1536 bits is implemented in a 0.18 um CMOS technology twice: once using the Split-Row method, and once using the Min-Sum algorithm for comparison. The Split-Row decoder operates at 53 MHz and delivers a throughput of 5.4 Gbps with 15 decoding iterations per block. The Split-Row decoder is about 1.3 times smaller, has an average wire length 1.5 times shorter, and has a throughput 1.6 times higher than the Min-Sum decoder.





Tinoosh Mohsenin, Bevan M. Baas. "Split-row: A reduced complexity, high throughput LDPC decoder architecture" In Proceedings of The IEEE International Conference of Computer Design (ICCD) , October 2006, pp. 320-325.

BibTeX entry

   author    = {Tinoosh Mohsenin and Bevan M. Baas},
   title     = {Split-row: A reduced complexity, high throughput LDPC decoder architecture},
   booktitle = {IEEE International Conference of Computer Design (ICCD)},
   month     = October,
   year      = 2006

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Last update: Oct 26, 2006