A Shared Memory Module for Asynchronous Arrays of Processors

Michael Meeuwsen
Zhiyi Yu
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555MHz and occupies 1.2mm2 in 0.18 um CMOS.



Michael Meeuwsen, Zhiyi Yu, Bevan M. Baas, "A Shared Memory Module for Asynchronous Arrays of Processors," EURASIP Journal on Embedded Systems, vol. 2007, Article ID 86273, 13 pages, 2007.

BibTeX entry

   author    = {Michael Meeuwsen and Zhiyi Yu and Bevan M. Baas},
   title     = {A Shared Memory Module for Asynchronous Arrays of Processors},
   journal   = {EURASIP Journal on Embedded Systems},
   year      = 2007,
   volume    = 2007,
   pages     = {Article ID 86273, 13 pages}

VCL Lab | ECE Dept. | UC Davis

Last update: May 14, 2007