An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder

Tinoosh Mohsenin
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


Low density parity check (LDPC) codes have received considerable attention due to their superior error correction performance, and emerging communication standards such as 10 Gigabit Ethernet (10GBASE-T), digital video broadcasting (DVB-S2) and WIMAX (802.16e) have adopted them.  Unfortunately, the codes inherently require irregular and global communication which leads to large wire-dominated circuits with low clock rates in high-speed systems that require many processing nodes.

Recently introduced "Split-Row" decoding algorithms and architectures increase parallelism compared to standard decoding methods and significantly reduce wire interconnect complexity. Three full-parallel decoder chips for a (2048,1723) LDPC code compliant with the 10GBASE-T standard using standard, Split-2 and Split-4 methods are implemented in 65 nm, 1.3 V, 7-metal-layer CMOS. The Split-4 decoder occupies 5.04 mm^2, operates at 133 MHz, delivers 18.2 Gbps throughput, and dissipates 833 mW at SNR=4.0 dB. The Split-4 decoder operates at 77.5 MHz, delivers 10.6 Gbps and dissipates 208 mW at 0.85 V. Compared to the standard decoder, this chip is 3.6 times smaller, has a clock rate and throughput 10.6 times higher, is 2.8 times more energy efficient at 1.3 V, and has an error performance degradation of only 0.5 dB.

Presentation Slides

VCL Lab | ECE Dept. | UC Davis

Last update: November 12, 2008