Recently introduced "Split-Row" decoding algorithms and architectures increase parallelism compared to standard decoding methods and significantly reduce wire interconnect complexity. Three full-parallel decoder chips for a (2048,1723) LDPC code compliant with the 10GBASE-T standard using standard, Split-2 and Split-4 methods are implemented in 65 nm, 1.3 V, 7-metal-layer CMOS. The Split-4 decoder occupies 5.04 mm^2, operates at 133 MHz, delivers 18.2 Gbps throughput, and dissipates 833 mW at SNR=4.0 dB. The Split-4 decoder operates at 77.5 MHz, delivers 10.6 Gbps and dissipates 208 mW at 0.85 V. Compared to the standard decoder, this chip is 3.6 times smaller, has a clock rate and throughput 10.6 times higher, is 2.8 times more energy efficient at 1.3 V, and has an error performance degradation of only 0.5 dB.
Last update: November 12, 2008