A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors

Abstract:

The globally asynchronous locally synchronous (GALS) design style for a large area chip has 
become increasingly attractive due to the difficulty of designing global clocking circuits 
at high clock frequencies in the GHz range. In this paper, we present a high-speed interconnect
network for a GALS multiprocessing system composed of a 2-D mesh array of processors. 
Processors are locally clocked by their own oscillators and communicate together using a static
circuit-switched technique combined with a source-synchronous communication scheme. A technique
to maximize the timing reliability on long-distance interconnects at high clock rates is 
proposed that is area and power efficient with low latency and allows a sustained ideal peak 
throughput of one word per cycle.

Paper

  PDF (198 KB),   (c) Copyright, 2009, IEEE

Poster

• PDF (586 KB),   (c) Copyright, 2009

Reference

Anh T. Tran, Dean N. Truong, Bevan M. Baas, "A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors" IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp.996-999.

BibTeX Entry

@INPROCEEDINGS{Tran:ISCAS,
   author={Tran, A.T. and Truong, D.N. and Baas, B.M.},
   booktitle={Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on}, 
   title={A low-cost high-speed source-synchronous interconnection technique for {GALS} chip multiprocessors},
   year={2009},
   month={May.},
   pages={996-999},
   doi={10.1109/ISCAS.2009.5117926}
}