High Throughput and Energy Efficient LDPC Decoders Using Multi-Split-Row Threshold Method
Tinoosh Mohsenin
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
Abstract:
Low density parity check (LDPC) codes have received
signicant attention due to their superior error correction performance,
and have been considered by emerging communication standards such
as 10 Gigabit Ethernet (10GBASE-T), digital video broadcasting (DVBS2),
WiMAX (802.16e), Wi-Fi (802.11n) and WPANs (802.15.3c). Due
to the codes' inherently irregular and global communication patterns,
high-speed systems that require many processing nodes typically suffer
from large wire dominated circuits with low clock rates. The recently
introduced Split-Row Threshold decoding algorithms and architectures
increase parallelism, signicantly reduce wire interconnect complexity,
and have a small increase in bit error rate compared to the standard
MinSum decoding algorithm. Several Multi-Split-Row Threshold
decoders have been implemented in 65 nm CMOS for a (2048,1723)
LDPC code compliant with the 10GBASE-T Ethernet standard. The
impact of different levels of partitioning on error performance, wire
interconnect complexity, decoder area, power dissipation and speed are
investigated. A 16-way Split-Row Threshold decoder occupies 3.8 mm^2,
runs at 101 MHz, delivers a throughput of 13.8 Gbps at 15 iterations,
and dissipates 318 mW at 1.3 V. Compared to a standard MinSum
decoder implemented in the same technology and physical design ow,
the presented chip is 3.9 times smaller, has a clock rate and throughput
6 times higher, is 4.4 times more energy efcient, and has an error
performance degradation of only 0.22 dB.
Paper
VCL Lab
| ECE Dept.
| UC Davis
Last update: Sept 22, 2009