Low Power LDPC Decoder with Efficient Stopping Scheme for Undecodable Blocks

Tinoosh Mohsenin
Houshmand Shirani-Mehr
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


An efficient technique for early detection of undecodable
blocks during LDPC decoding is introduced. The
proposed method avoids unnecessary decoding iterations by
predicting decoding failure and therefore results in significant
improvement in power and latency in low SNR values. The
proposed method which has a low hardware overhead compares
the parity checksum against predefined threshold values
for three iterations and terminates decoding if a condition is
met. A 5.25 mm2 10GBASE-T Split-Row Threshold decoder is
implemented using the proposed technique in 65 nm CMOS.
The postlayout results show that at low SNR value of 3.0 dB,
the decoder requires 2.3 times fewer decoding iterations which
results in 23 pJ/bit energy dissipation. This is 2.4 times lower than
the energy dissipation of Split-Row Threshold decoder without
the proposed early stopping technique.




T. Mohsenin, H. Shirani-Mehr and B. Baas, "Low Power LDPC Decoder with Efficient Stopping Scheme for Undecodable Blocks" IEEE International Symposium on Circuits and Systems (ISCAS'11), May 2011, pp..

BibTeX Entry

    author={Mohsenin, T. and Shirani-Mehr, H. and Baas, B.},
    booktitle={Circuits and Systems, 2011. ISCAS 2011. IEEE International Symposium on}, 
    title={Low Power {LDPC} Decoder with Efficient
Stopping Scheme for Undecodable Blocks},

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Last update: May 28, 2011