Toward More Accurate Scaling Estimates of CMOS Circuits from 180 nm to 22 nm

Abstract:

With deep submicron technology nodes other methods are needed to obtain scaling factors rather
than the traditional scaling factors which held for the pre-submicron era. This work presents
scaling factors between major technology nodes between 180 nm and 22 nm operating at voltages from
1.8 V to 0.7 V. Common operating data for these technologies were taken from the International
Technology Roadmap for Semiconductors (IRTS). HSpice simulations that rely on the Predictive
Technology Model (PTM) for transistor characteristics were used to find the scaling factors.

Paper

  PDF (494 KB),   (c) Copyright, 2011, University of California, Davis

Reference

Aaron Stillmaker, Zhibin Xiao and Bevan M. Baas,
"Toward More Accurate Scaling Estimates of CMOS Circuits from 180 nm to 22 nm,"
Technical Report ECE-VCL-2011-4 VLSI Computation Lab, ECE Department, University of California, Davis, December, 2011.

BibTeX Entry

@techreport{astill:techscaling,
        author = {Aaron Stillmaker and Zhibin Xiao and Bevan Baas},
        title = {Toward More Accurate Scaling Estimates of CMOS Circuits from 180~nm to 22~nm},
        institution = {VLSI Computation Lab, ECE Department, University of California, Davis},
        year = 2011,
        month = dec,
        number = {ECE-VCL-2011-4},
	note = {\url{http://www.ece.ucdavis.edu/cerl/techreports/2011-4/}}
}