Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms

Mohammad H. Foroozannejad
Matin Hashemi*
Alireza Mahini**
Bevan M. Baas
Soheil Ghiasi

Department of Electrical and Computer Engineering
University of California, Davis

*Department of Electrical Engineering
Sharif University of Technology

**Department of Computer Engineering
Islamic Azad University

Abstract:

We study the problem of mapping concurrent tasks of an application to cores of a chip multiprocessor that utilize circuit-switched interconnect and global asynchronous local synchronous (GALS) clocking domains. We develop a configurable algorithm that naturally handles a number of practical requirements, such as architectural features of the target platform, core failures, and hardware accelerators, and in addition, is scalable to a large number of tasks and cores. Experiments with several real life applications show that our algorithm outperforms manual mapping, integer linear programming-based mapping after ten days of solver run time, and a recent packet-switched network on chip-based task mapper through which, we underscore the unique requirements of task mapping for circuit-switched GALS architectures.

Paper

Reference

Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, and Soheil Ghiasi "Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms," IEEE Transactions on Computer-Aided Design of Integrated Circuit Circuits and Systems, vol. 33, no. 5, pp. 752-762, May 2014.

BibTeX Entry


@article{foroozannejad:TCAD2014:mapping,
   author  = {M. H. Foroozannejad and M. Hashemi and A. Mahini and B. M. Baas and S. Ghiasi},
   journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuit Circuits and Systems}, 
   title   = {Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms},
   year    = 2014,
   month   = may,
   volume  = 62,
   number  = 3,
   pages   = 536--547
   }
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