Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation

Jon J. Pimentel
Aaron Stillmaker
Brent Bohnenstiehl
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

The widths of data words in digital processors have a direct impact on area in application-specific ICs (ASICs) and FPGAs. Circuit area impacts energy dissipation per workload and chip cost. Floatingpoint exponent and mantissa widths are independently varied for the seven major computational blocks of an airborne synthetic aperture radar (SAR) engine. The circuit area in 65 nm CMOS and the PSNR and SSIM metrics are found for 572 design points. With word-width reductions of 46.9–79.7%, images with a 0.99 SSIM are created with imperceptible image quality degradation and a 1.9–11.4x area reduction.

Paper

Reference

Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl and Bevan M. Baas, "Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation," IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC) Nov. 2015.

BibTeX Entry

@INPROCEEDINGS{Pimentel:ACSSC2015,
   author    = {Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl and Bevan M. Baas},
   booktitle = {IEEE Asilomar Conference on Signals, Systems and Computers ({ACSSC})}, 
   title     = {Area Efficient Backprojection Computation with Reduced Floating-Point Word Width for SAR Image Formation},
   year      = 2015,
   month     = nov
   }
VCL Lab | ECE Dept. | UC Davis

Last update: December 8, 2014