A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32nm 1000-Processor Array

Brent Bohnenstiehl
Aaron Stillmaker
Jon J. Pimentel
Timothy Andreas
Bin Liu
Anh T. Tran
Emmanuel Adeagbo
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32 nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.

Paper

Reference

Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas, "A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32nm 1000-Processor Array," Symposium on VLSI Circuits, Honolulu, HI, June 2016.

BibTeX Entry

@inproceedings{bohnenstiehl:vlsi2016,
   author    = {B. Bohnenstiehl and A. Stillmaker and J. Pimentel and
               T. Andreas and B. Liu and A. Tran and E. Adeagbo and
               B. Baas},
   booktitle = {Symposium on {VLSI} Circuits},
   title     = {A 5.8~{p{J}/{O}p} 115~Billion~{O}ps/sec, to
               1.78~Trillion~{O}ps/sec 32~nm 1000-Processor Array},
   year      = 2016,
   month     = jun
   }
VCL Lab | ECE Dept. | UC Davis

Last update: June 18, 2016