Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm

Aaron Stillmaker
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

Classical scaling equations which estimate parameters such as circuit delay and energy per operation across technology generations have been extremely useful for predicting performance metrics as well as for comparing designs across fabrication technologies. Unfortunately in the CMOS deep-submicron era, the classical scaling equations are becoming increasingly less accurate and new practical scaling methods are needed. We curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models. While the classical scaling equations give differences as much as 83× from the predictions of PTM and ITRS models, our predictive polynomial models with table-based coefficients yield a coefficient of determination, or R2, value of greater than 0.95.

Paper

Reference

Aaron Stillmaker and Bevan M. Baas,
"Scaling Equations for the Accurate Prediction of CMOS Device Performance from 180 nm to 7 nm,"
Integration, the VLSI Journal, vol. 58, pp. 74–81, June 2017.

BibTeX Entry

@article{Stillmaker201774,
   author    = {A. Stillmaker and B. Baas},
   title     = {Scaling equations for the accurate prediction of {CMOS} device
                performance from 180 nm to 7 nm},
   journal   = {Integration, the {VLSI} Journal},
   volume    = 58,
   pages     = {74--81},
   year      = 2017,
   note      = {\url{http://vcl.ece.ucdavis.edu/pubs/2017.02.VLSIintegration.TechScale/}}
   }

VCL Lab | ECE Dept. | UC Davis

Last update: Apr. 7, 2017