Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding

Shifu Wu 1
Snelata Gutgutia 2
Massimo Alioto 2
Bevan M. Baas 1

  1. VLSI Computation Laboratory
    Department of Electrical and Computer Engineering
    University of California, Davis
  2. GREEN IC Group
    Department of Electrical and Computer Engineering
    National University of Singapore

Abstract:

The Display Stream Compression (DSC) standard enables visually-lossless video compression with a much lower hardware cost than H.264 and HEVC albeit with a lower level of compression. We present the first published DSC encoder architectures—including a Single Slice architecture which supports one slice per line encoding and a Slice Interleaving architecture which supports one or more slices per line. Seven designs that fully support the DSC v1.2a standard have been implemented and synthesized in a 28 nm CMOS standard cell library. The designs are able to perform real-time encoding at frame rates up to 35–40 frames per second (fps) for 8K UHD (7680X4320), 140–160 fps for 4K UHD (3840X2160), and 560–642 fps for 1080p (1920X1080) video in 4:4:4 mode. In native 4:2:2 and 4:2:0 modes, frame rates are doubled to 70–80 fps, 280–320 fps and 1120–1284 fps for 8K UHD, 4K UHD and 1080p, respectively. The designs require 194 K–433 K minimum-sized NAND2 equivalent gates and main memory of 31.9–68.5 KB to support 8K UHD.

Paper

Reference

Shifu Wu, Snehlata Gutgutia, Massimo Alioto and Bevan M. Baas, "Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding," IEEE Asilomar Conference on Signals, Sysems and Computers (ACSSC), Oct. 2018.

BibTeX Entry

@INPROCEEDINGS{Wu:ACSSC2018,
   author={Shifu Wu, Snehlata Gutgutia, Massimo Alioto and Bevan M. Baas},
   booktitle={IEEE Asilomar Conference on Signals, Sysems and Computers ({ACSSC})}, 
   title={Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding},
   year={2018},
   month={Oct.}
}
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Last update: Dec. 04, 2018