This thesis presents the design of a dynamically configurable Fast Fourier Transform (FFT) processor built around a continuous flow, mixed-radix architecture. Complex FFTs/inverse FFTs (IFFTs) of size 16 to 4096-point can be performed, with the option to turn on/off block floating point (BFP), and to divide the input data by 2 (to prevent overflow in the butterfly). An addressing scheme is presented to accomodate performing FFTs of any size. Minimizing twiddle factor data storage is discussed with a method to improve FFT accuracy and reduce the number of multiplications performed within an FFT. The datapath for this processor varies between 16 to 34-bits. Built in a 65 nm technology, a 1024-point FFT is performed in 1.29 μs and a 4096-point FFT is performed in 6.11 μs at a clock speed of 1.01 GHz. The accuracy is 80 dB for a 64-point FFT and 73 dB for a 1024-point random-data FFT. The processor consumes 250 mW at 1.3 V, and takes up an area of 1.01 mm2.
Anthony T. Jacobson, "A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT Processor," Technical Report ECE-CE-2007-3, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.
@mastersthesis{toney:msthesis,
author = {Anthony T. Jacobson},
title = {A Continuous-Flow Mixed-Radix Dynamically-Configurable FFT
Processor},
school = {University of California},
year = 2007,
address = {Davis, CA, USA},
month = jul,
note = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2007-3}}
}