Due to advances in VLSI technology large scale parallel arrays are being developed at a rapid rate and growing larger in size with each new chip fabricated. Programming these large scale parallel arrays using fully manual techniques is very difficult as the array size grows larger. In this work we present a framework for mapping arbitrarily connected task graphs onto nearest neighbor dominated 2D-mesh parallel arrays. The contributions are an automated mapping algorithm, for placing and routing applications onto parallel arrays, and an intuitive graphical user interface, for creating applications based on their dataflow. In this work we demonstrate how an automated mapping algorithm is essential for efficiently programming large scale parallel arrays. The Asynchronous Array of Simple Processors (AsAP) architecture is used as a test platform for the mapping algorithm, but the mapping algorithm can easily be adapted to other parallel array architectures. The mapping algorithm is time efficient, scalable up to thousands of processors, tolerant of fabrication errors, and can even optimize applications using processor characteristics. Other features include, configurable architectural parameters, customizable user cost functions, and dynamically inserted routing processors which handle intersecting datastreams.
Eric W. Work, "Algorithms and Software Tools for Mapping Arbitrarily Connected Tasks onto an Asynchronous Array of Simple Processors," Technical Report ECE-CE-2007-4, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2007.
@mastersthesis{ewwork:msthesis,
author = {Eric W. Work},
title = {Algorithms and Software Tools for Mapping Arbitrarily
Connected Tasks onto an Asynchronous Array of Simple
Processors},
school = {University of California},
year = 2007,
address = {Davis, CA, USA},
month = Sep,
note = {\url{http://www.ece.ucdavis.edu/vcl/pubs/theses/2007-4}}
}