AsAPV2 No. 1 Signal Delay Values

AsAPV2 No. 1 Signal IODELAY Taps:

Matched Length Group #1: SIG_DML1_CON, Reference Signal: FPGA_ASAP1_CLK_OUT
Matched Length Group #2: SIG_DML2_CON, Reference Signal: FPGA_ASAP1_CLK_IN

AsAPV2 No. 1 Signal Delay Values
Signal Name	Length (Mils)	ML Group	Is Reference	Average Length (Mils)	Length (ps)	Added Delay (ps)	Number of Taps Needed	Number of Taps Needed (Normalized)
Matched Length Group #1
FPGA_ASAP1_VLD_OUT	4049.7	SIG_DML1_CON	0	3777.07	676.2999	-26.99889	0	1
FPGA_ASAP1_REQ_OUT	4052.61	SIG_DML1_CON	0	3777.07	676.78587	-27.48486	0	1
FPGA_ASAP1_DATA_OUT15	4144.88	SIG_DML1_CON	0	3777.07	692.19496	-42.89395	0	1
FPGA_ASAP1_DATA_OUT14	4209.27	SIG_DML1_CON	0	3777.07	702.94809	-53.6470800000001	0	1
FPGA_ASAP1_DATA_OUT13	4166.49	SIG_DML1_CON	0	3777.07	695.80383	-46.5028199999999	0	1
FPGA_ASAP1_DATA_OUT12	3939.19	SIG_DML1_CON	0	3777.07	657.84473	-8.54372000000001	0	1
FPGA_ASAP1_DATA_OUT11	4805.99	SIG_DML1_CON	0	3777.07	802.60033	-153.29932	-1	0
FPGA_ASAP1_DATA_OUT10	4815.56	SIG_DML1_CON	0	3777.07	804.19852	-154.89751	-1	0
FPGA_ASAP1_DATA_OUT9	3641.68	SIG_DML1_CON	0	3777.07	608.16056	41.14045	0	1
FPGA_ASAP1_DATA_OUT8	3701.51	SIG_DML1_CON	0	3777.07	618.15217	31.14884	0	1
FPGA_ASAP1_DATA_OUT7	4163.47	SIG_DML1_CON	0	3777.07	695.29949	-45.9984800000001	0	1
FPGA_ASAP1_DATA_OUT6	4227.27	SIG_DML1_CON	0	3777.07	705.95409	-56.65308	0	1
FPGA_ASAP1_DATA_OUT5	3559.15	SIG_DML1_CON	0	3777.07	594.37805	54.92296	0	1
FPGA_ASAP1_DATA_OUT4	3785.44	SIG_DML1_CON	0	3777.07	632.16848	17.13253	0	1
FPGA_ASAP1_DATA_OUT3	3856.54	SIG_DML1_CON	0	3777.07	644.04218	5.25882999999999	0	1
FPGA_ASAP1_DATA_OUT2	4078	SIG_DML1_CON	0	3777.07	681.026	-31.72499	0	1
FPGA_ASAP1_DATA_OUT1	3278.86	SIG_DML1_CON	0	3777.07	547.56962	101.73139	1	2
FPGA_ASAP1_DATA_OUT0	3288.72	SIG_DML1_CON	0	3777.07	549.21624	100.08477	1	2
FPGA_ASAP1_CLK_OUT	3888.03	SIG_DML1_CON	1	3777.07	649.30101	0	0	1
Matched Length Group #2
FPGA_ASAP1_VLD_IN	2137.68	SIG_DML2_CON	0	2638.49210526316	356.99256	86.673	1	3
FPGA_ASAP1_REQ_IN	2767.24	SIG_DML2_CON	0	2638.49210526316	462.12908	-18.46352	0	2
FPGA_ASAP1_DATA_IN15	2695.18	SIG_DML2_CON	0	2638.49210526316	450.09506	-6.42950000000002	0	2
FPGA_ASAP1_DATA_IN14	2657.36	SIG_DML2_CON	0	2638.49210526316	443.77912	-0.113560000000064	0	2
FPGA_ASAP1_DATA_IN13	2342.88	SIG_DML2_CON	0	2638.49210526316	391.26096	52.4045999999999	0	2
FPGA_ASAP1_DATA_IN12	2361.73	SIG_DML2_CON	0	2638.49210526316	394.40891	49.2566499999999	0	2
FPGA_ASAP1_DATA_IN11	2188.27	SIG_DML2_CON	0	2638.49210526316	365.44109	78.2244699999999	1	3
FPGA_ASAP1_DATA_IN10	2183.37	SIG_DML2_CON	0	2638.49210526316	364.62279	79.04277	1	3
FPGA_ASAP1_DATA_IN9	2551.92	SIG_DML2_CON	0	2638.49210526316	426.17064	17.4949199999999	0	2
FPGA_ASAP1_DATA_IN8	2961.36	SIG_DML2_CON	0	2638.49210526316	494.54712	-50.8815600000001	0	2
FPGA_ASAP1_DATA_IN7	2636.86	SIG_DML2_CON	0	2638.49210526316	440.35562	3.30993999999993	0	2
FPGA_ASAP1_DATA_IN6	2601.93	SIG_DML2_CON	0	2638.49210526316	434.52231	9.14324999999997	0	2
FPGA_ASAP1_DATA_IN5	3023.82	SIG_DML2_CON	0	2638.49210526316	504.97794	-61.3123800000001	0	2
FPGA_ASAP1_DATA_IN4	3355.69	SIG_DML2_CON	0	2638.49210526316	560.40023	-116.73467	-1	1
FPGA_ASAP1_DATA_IN3	3219.09	SIG_DML2_CON	0	2638.49210526316	537.58803	-93.92247	-1	1
FPGA_ASAP1_DATA_IN2	3142.93	SIG_DML2_CON	0	2638.49210526316	524.86931	-81.2037500000001	-1	1
FPGA_ASAP1_DATA_IN1	3586.95	SIG_DML2_CON	0	2638.49210526316	599.02065	-155.35509	-1	1
FPGA_ASAP1_DATA_IN0	3717.09	SIG_DML2_CON	0	2638.49210526316	620.75403	-177.08847	-2	0
FPGA_ASAP1_CLK_IN	2656.68	SIG_DML2_CON	1	2638.49210526316	443.66556	0	0	2