AsAPV2 No. 2 Signal Delay Values

AsAPV2 No. 2 Signal IODELAY Taps:

Matched Length Group #1: SIG_DML1_CON, Reference Signal: FPGA_ASAP2_CLK_OUT
Matched Length Group #2: SIG_DML2_CON, Reference Signal: FPGA_ASAP2_CLK_IN

AsAPV2 No. 2 Signal Delay Values
Signal Name	Length (Mils)	ML Group	Is Reference	Average Length (Mils)	Length (ps)	Added Delay (ps)	Number of Taps Needed	Number of Taps Needed (Normalized)
Matched Length Group #1
FPGA_ASAP2_VLD_OUT	5298.4	SIG_DML1_CON	0	4964.46894736842	884.8328	17.4565100000001	0	1
FPGA_ASAP2_REQ_OUT	5138.41	SIG_DML1_CON	0	4964.46894736842	858.11447	44.1748400000001	0	1
FPGA_ASAP2_DATA_OUT15	5198.95	SIG_DML1_CON	0	4964.46894736842	868.22465	34.0646600000001	0	1
FPGA_ASAP2_DATA_OUT14	5282.13	SIG_DML1_CON	0	4964.46894736842	882.11571	20.1736000000001	0	1
FPGA_ASAP2_DATA_OUT13	5487.81	SIG_DML1_CON	0	4964.46894736842	916.46427	-14.1749600000001	0	1
FPGA_ASAP2_DATA_OUT12	5680.78	SIG_DML1_CON	0	4964.46894736842	948.69026	-46.4009499999999	0	1
FPGA_ASAP2_DATA_OUT11	5874.91	SIG_DML1_CON	0	4964.46894736842	981.10997	-78.8206599999999	-1	0
FPGA_ASAP2_DATA_OUT10	5837.32	SIG_DML1_CON	0	4964.46894736842	974.83244	-72.5431299999999	0	1
FPGA_ASAP2_DATA_OUT9	4944.92	SIG_DML1_CON	0	4964.46894736842	825.80164	76.4876700000001	0	1
FPGA_ASAP2_DATA_OUT8	4669.31	SIG_DML1_CON	0	4964.46894736842	779.77477	122.51454	1	2
FPGA_ASAP2_DATA_OUT7	5679.63	SIG_DML1_CON	0	4964.46894736842	948.49821	-46.2089	0	1
FPGA_ASAP2_DATA_OUT6	5282.01	SIG_DML1_CON	0	4964.46894736842	882.09567	20.1936400000001	0	1
FPGA_ASAP2_DATA_OUT5	4691.11	SIG_DML1_CON	0	4964.46894736842	783.41537	118.87394	1	2
FPGA_ASAP2_DATA_OUT4	4599.08	SIG_DML1_CON	0	4964.46894736842	768.04636	134.24295	1	2
FPGA_ASAP2_DATA_OUT3	5928.96	SIG_DML1_CON	0	4964.46894736842	990.13632	-87.84701	-1	0
FPGA_ASAP2_DATA_OUT2	5494.71	SIG_DML1_CON	0	4964.46894736842	917.61657	-15.3272599999999	0	1
FPGA_ASAP2_DATA_OUT1	4679.77	SIG_DML1_CON	0	4964.46894736842	781.52159	120.76772	1	2
FPGA_ASAP2_DATA_OUT0	4556.7	SIG_DML1_CON	0	4964.46894736842	760.9689	141.32041	1	2
FPGA_ASAP2_CLK_OUT	5402.93	SIG_DML1_CON	1	4964.46894736842	902.28931	0	0	1
Matched Length Group #2
FPGA_ASAP2_VLD_IN	4551.79	SIG_DML2_CON	0	4913.59842105263	760.14893	95.9164500000001	1	3
FPGA_ASAP2_REQ_IN	4173.06	SIG_DML2_CON	0	4913.59842105263	696.90102	159.16436	2	4
FPGA_ASAP2_DATA_IN15	4780.52	SIG_DML2_CON	0	4913.59842105263	798.34684	57.71854	0	2
FPGA_ASAP2_DATA_IN14	4717.12	SIG_DML2_CON	0	4913.59842105263	787.75904	68.3063400000001	0	2
FPGA_ASAP2_DATA_IN13	4786.03	SIG_DML2_CON	0	4913.59842105263	799.26701	56.7983700000001	0	2
FPGA_ASAP2_DATA_IN12	4730.52	SIG_DML2_CON	0	4913.59842105263	789.99684	66.06854	0	2
FPGA_ASAP2_DATA_IN11	4767.18	SIG_DML2_CON	0	4913.59842105263	796.11906	59.94632	0	2
FPGA_ASAP2_DATA_IN10	4904.3	SIG_DML2_CON	0	4913.59842105263	819.0181	37.04728	0	2
FPGA_ASAP2_DATA_IN9	5335.07	SIG_DML2_CON	0	4913.59842105263	890.95669	-34.8913099999999	0	2
FPGA_ASAP2_DATA_IN8	5698.97	SIG_DML2_CON	0	4913.59842105263	951.72799	-95.66261	-1	1
FPGA_ASAP2_DATA_IN7	5019.04	SIG_DML2_CON	0	4913.59842105263	838.17968	17.8857	0	2
FPGA_ASAP2_DATA_IN6	4888.85	SIG_DML2_CON	0	4913.59842105263	816.43795	39.62743	0	2
FPGA_ASAP2_DATA_IN5	5732.7	SIG_DML2_CON	0	4913.59842105263	957.3609	-101.29552	-1	1
FPGA_ASAP2_DATA_IN4	5651.11	SIG_DML2_CON	0	4913.59842105263	943.73537	-87.6699899999999	-1	1
FPGA_ASAP2_DATA_IN3	5832.44	SIG_DML2_CON	0	4913.59842105263	974.01748	-117.9521	-1	1
FPGA_ASAP2_DATA_IN2	5564.81	SIG_DML2_CON	0	4913.59842105263	929.32327	-73.25789	0	2
FPGA_ASAP2_DATA_IN1	6143.62	SIG_DML2_CON	0	4913.59842105263	1025.98454	-169.91916	-2	0
FPGA_ASAP2_DATA_IN0	6081.24	SIG_DML2_CON	0	4913.59842105263	1015.56708	-159.5017	-2	0
FPGA_ASAP2_CLK_IN	5126.14	SIG_DML2_CON	1	4913.59842105263	856.06538	0	0	2