AsAP: An Asynchronous Array of Simple Processors

Zhiyi Yu
Michael Meeuwsen
Ryan Apperson
Omar Sattari
Michael Lai
Jeremy Webb
Eric Work
Dean Truong
Tinoosh Mohsenin
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


An array of simple programmable processors is implemented in
0.18 m CMOS and contains 36 asynchronously clocked independent
processors. Each processor occupies 0.66 mm^2 and is fully 
functional at a clock rate of 520-540 MHz at 1.8 V and over 
600 MHz at 2.0 V. Processors dissipate an average of 32 mW 
under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 
0.9 V and 116 MHz while executing applications such as a 
JPEG encoder core and a fully compliant IEEE 802.11a/g 
wireless LAN baseband transmitter.



Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas, "AsAP: An Asynchronous Array of Simple Processors," IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

BibTeX Entry

   author={Zhiyi Yu and Meeuwsen, M.J. and Apperson, R.W. and Sattari, O. and Lai, M. and Webb, J.W. and Work, E.W. and Truong, D. and Mohsenin, T. and Baas, B.M.},
   journal={Solid-State Circuits, IEEE Journal of}, 
   title={{AsAP}: An Asynchronous Array of Simple Processors},

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Last update: Sep. 27, 2010