A Complete Real-Time 802.11a Baseband Receiver Implemented on an Array of Programmable Processors

Anh T. Tran
Dean N. Truong
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


This paper reports the design and software implementation of a real-time digital baseband 
receiver compliant with the IEEE 802.11a standard on the AsAP2 platform, a DSP chip 
multiprocessor. The computational platform consists of an array of programmable 
processors and configurable accelerators interconnected in a 2-D mesh network that are 
well matched for implementing complex DSP and embedded systems such as wireless and 
video applications. The receiver has full functionality including frame detection, timing 
synchronization, carrier frequency offset compensation, and channel equalization. 
It supports all eight operational modes defined in the standard: 
6, 9, 12, 18, 24, 36, 48 and 54 Mbps. The implementation is optimized such that the 
receiver can obtain a full 54 Mbps rate while using an array of 29 small processors 
plus Viterbi and FFT accelerators configured to operate at 590 MHz.


Presentation Slides


Anh T. Tran, Dean N. Truong, and Bevan M. Baas, "A Complete Real-Time 802.11a Baseband Receiver Implemented on an Array of Programmable Processors." Asilomar Conference on Signals, Systems and Computers (ACSSC), October 2008, pp. 165-170.

BibTeX Entry

    author={Tran, A.T. and Truong, D.N. and Baas, B.M.},
    booktitle={Signals, Systems and Computers, 2008 42nd Asilomar Conference on}, 
    title={A complete real-time 802.11a baseband receiver implemented on an array of programmable processors},

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Last update: Sep. 27, 2010