Multi-Split-Row Threshold Decoding Implementations for LDPC Codes

Tinoosh Mohsenin
Dean Truong
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


The recently introduced Split-Row Threshold algorithm
significantly improves the error performance when compared to the non-
threshold Split-Row algorithm while requiring a very small increase in
hardware complexity. The Multi-Split-Row Threshold decoding algorithm
presented in this paper enables further reductions in routing complexity
for greater throughput and smaller circuit area implementations. Several
Multi-Split-Row Threshold decoder designs have been implemented in
65 nm CMOS and the impact of the different levels of partitioning on
error performance, wire interconnect complexity, decoder area, and speed
are investigated. The Split-Row-16 Threshold decoder occupies 3.8 mm^2,
runs at 101 MHz, delivers a throughput of 13.8 Gbps at 15 iterations and
is only 0.28 dB and 0.22 dB away from SPA and MinSum Normalized.




T. Mohsenin, D. Truong and B. Baas, "Multi-Split-Row Threshold Decoding Implementations for LDPC Codes" IEEE International Symposium on Circuits and Systems (ISCAS'09), May 2009, pp. 2449-2452.

BibTeX Entry

    author={Mohsenin, T. and Truong, D. and Baas, B.},
    booktitle={Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on}, 
    title={Multi-Split-Row Threshold decoding implementations for {LDPC} codes},

VCL Lab | ECE Dept. | UC Davis

Last update: Sep. 27, 2010