Trends and Challenges in LDPC Hardware Decoders

Tinoosh Mohsenin
Bevan Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


Over the last decade low density parity check (LDPC) codes have received 
significant attention due to their superior error correction performance, 
and have been adopted by recent communication standards such as 10 Gigabit 
Ethernet (10GBASE-T), digital video broadcasting (DVB-S2), WiMAX (802.16e),
Wi-Fi (802.11n) and 60 GHz WPAN (802.15.3c). While there has been much
research on LDPC decoders and their VLSI implementations, many diffculties
to achieve requirements remain such as lower error floors, reduced 
interconnect complexities, smaller die areas, lower power dissipation, and
design reconfigurability (run-time) to support multiple code lengths and 
code rates.

This paper provides an overview of current research in LDPC decoder algorithms and architectures that are well suited for hardware implementations. Near and long-term trends of next generation LDPC requirements are made and an analysis of how current architectures will fare with the increasing demands on throughput, BER performance, power dissipation, and chip area (among others) that will be necessary for the widespread adoption of LDPC codecs in near-future applications.



Mohsenin, T.; Baas, B.; , "Trends and challenges in LDPC hardware decoders," Signals, Systems and Computers, 2009 Conference Record of the Forty-Third Asilomar Conference on, pp.1273-1277, Nov. 2009.

BibTeX Entry

   author={Mohsenin, T. and Baas, B.},
   booktitle={Signals, Systems and Computers, 2009 Conference Record of the Forty-Third Asilomar Conference on},
   title={Trends and challenges in {LDPC} hardware decoders},

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Last update: Sep. 27, 2010