RoShaQ: High-Performance On-Chip Router with Shared Queues

Anh T. Tran
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Best Paper Award at the 29th IEEE International Conference on Computer Design (ICCD), 2011.


On-chip router typically has buffers dedicated to its input or output ports for temporarily storing packets in case contention occurs on output physical channels. Buffers, unfortunately, consume significant portions of router area and power. While running a traffic trace, however, not all input ports of routers have incoming packets needed to be transferred at the same time. As a result, a large number of buffer queues in the network are empty while other queues are mostly busy. This observation motivates us to design RoShaQ, a router architecture that maximizes buffer utilization by allowing to share multiple buffer queues among input ports. Sharing queues, in fact, makes using buffers more efficient hence is able to achieve higher throughput when the network load becomes heavy. On the other side, at light traffic load, our router achieves low latency by allowing packets to effectively bypass these shared queues. Experimental results show that RoShaQ is 21% less latency and 14% higher saturation throughput than a typical virtual-channel (VC) router with 4% higher power and 16% larger area. Due to its higher performance, RoShaQ consumes 7% less energy per a transferred packet than a VC router given the same buffer space capacity.



A. T. Tran and B. M. Baas, "RoShaQ: High-Performance On-Chip Router with Shared Queues," IEEE International Conference on Computer Design (ICCD), Oct. 2011, pp. 232-238.

BibTeX Entry

   author    = {Anh T. Tran and Bevan M. Baas},
   booktitle = {IEEE International Conference on Computer Design ({ICCD})},
   title     = {{RoShaQ}: High-Performance On-Chip Router with Shared Queues},
   year      = 2011,
   month     = oct,
   pages     = {232--238}

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Last update: Oct. 14, 2011