NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip

Abstract:

As the number of processing elements (PE) on a single chip increases with each 
generation of CMOS technology, network on-chip (NoC) has become a de-facto 
communication fabric for these PEs. Due to high design and test costs for real 
many-core chips, simulators which allow exploring the best design options for
systems before actually building them have been becoming highly necessary in system 
design and optimization flows. This paper presents NoCTweak, a highly parameterizable 
NoC simulator used for early exploration of performance and energy efficiency of 
on-chip networks. The simulator has been developed in SystemC, a C++ plugin, which 
allows fast modeling of concurrent hardware modules at the cycle-level accuracy. 
The statistic output results provided by the simulator are the average network 
latency, throughput, router power and energy per transferred data packet 
corresponding to a given network configuration, a certain traffic pattern and load. 
Area, timing and power of router components are post-layout data based on 
standard-cell libraries.

Paper

  PDF (155 KB),   (c) Copyright, 2012, University of California, Davis

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Reference

Anh T. Tran and Bevan M. Baas,
"NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip,"
Technical Report ECE-VCL-2012-2, VLSI Computation Lab, ECE Department, University of California, Davis, July, 2012.

BibTeX Entry

@techreport{Tran:NoCTweak:2012,
        author = {Anh T. Tran and Bevan Baas},
        title = {NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip},
        institution = {VLSI Computation Lab, ECE Department, University of California, Davis},
        year = 2012,
        month = July,
        number = {ECE-VCL-2012-2},
	note = {\url{http://www.ece.ucdavis.edu/vcl/pubs/2012.07.techreport.noctweak/}}
}