Parallel AES Encryption Engines for Many-Core Processor Arrays

Bin Liu
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. The smallest design utilizes only 6 cores for offline key expansion and 8 cores for online key expansion, while the largest requires 107 cores and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency. Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.

Paper

Reference

Bin Liu and Bevan M. Baas, "Parallel AES Encryption Engines for Many-Core Processor Arrays," IEEE Transactions on Computers, vol. 62, no. 3, pp. 536-547, March 2013.

BibTeX Entry


@ARTICLE{LIU:AES,
  author={Bin Liu and Bevan M. Baas},
  journal={Computers, IEEE Transactions on}, 
  title={Parallel {AES} Encryption Engines for Many-Core Processor Arrays},
  year={2013},
  month={march},
  volume={62},
  number={3},
  pages={536--547},
  doi={10.1109/TC.2011.251},
  ISSN={0018-9340},
}
VCL Lab | ECE Dept. | UC Davis

Last update: Feb. 11, 2013