Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder

Renjie Chen
Masters Thesis
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
VLSI Computation Laboratory, University of California, Davis, 2019.

Abstract

Thesis

Reference

BibTeX entry

@mastersthesis{peiyao:vcl:mastersthesis,
   author      = {Renjie Chen},
   title       = {Architecture and Hardware for a 1 Bin per Cycle Context-Adaptive Binary Arithmetic Coder ({CABAC}) Encoder},
   school      = {University of California, Davis},
   year        = 2019,
   month       = dec,
   address     = {Davis, CA, USA},
   note        = {\url{http://vcl.ece.ucdavis.edu/pubs/theses/2019-3.renjie/}}
   }

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