A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors

Anh T. Tran
Dean N. Truong
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis


The globally asynchronous locally synchronous (GALS) design style for a large area chip has 
become increasingly attractive due to the difficulty of designing global clocking circuits 
at high clock frequencies in the GHz range. In this paper, we present a high-speed interconnect
network for a GALS multiprocessing system composed of a 2-D mesh array of processors. 
Processors are locally clocked by their own oscillators and communicate together using a static
circuit-switched technique combined with a source-synchronous communication scheme. A technique
to maximize the timing reliability on long-distance interconnects at high clock rates is 
proposed that is area and power efficient with low latency and allows a sustained ideal peak 
throughput of one word per cycle.




Anh T. Tran, Dean N. Truong, Bevan M. Baas, "A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors" IEEE International Symposium on Circuits and Systems (ISCAS), May 2009, pp.996-999.

BibTeX Entry

   author={Tran, A.T. and Truong, D.N. and Baas, B.M.},
   booktitle={Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on}, 
   title={A low-cost high-speed source-synchronous interconnection technique for {GALS} chip multiprocessors},

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