Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core

Jon J. Pimentel
Bevan M. Baas

VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Best Student Paper Award, Third Place at the 48th IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), 2014.

Abstract:

This paper proposes Hybrid Floating-Point Modules (HFPMs) as a method to improve software floating-point (FP) throughput without incurring the area overhead of hardware floating-point units (FPUs). The proposed HFPMs were synthesized in 65 nm CMOS. They increase throughput over a fixed-point software FP implementation by 3.6x for addition/subtraction, 2.3x for multiplication, and require less area than hardware modules. Nine functionally equivalent FPU implementations using combinations of software, hardware, and hybrid modules are synthesized and provide 1.07–3.34x higher throughput than a software FPU implementation, while requiring 1.08–12.5x less area than a hardware FPU for multiply-add operations.

Paper

Poster

Reference

Jon J. Pimentel and Bevan M. Baas, "Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core," IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC) Nov. 2014.

BibTeX Entry

@INPROCEEDINGS{Pimentel:ACSSC2014,
   author    = {Jon J. Pimentel and Bevan M. Baas},
   booktitle = {IEEE Asilomar Conference on Signals, Systems and Computers ({ACSSC})}, 
   title     = {Hybrid Floating-Point Modules with Low Area Overhead on a Fine-Grained Processing Core},
   year      = 2014,
   month     = nov
   }
VCL Lab | ECE Dept. | UC Davis

Last update: December 8, 2014