[VLSI Computation Lab]

The VLSI Computation Laboratory (VCL) is part of the ECE Department at the University of California at Davis. Our goal is to discover and develop novel contributions in high-performance, energy-efficient, and area-efficient VLSI computation with an emphasis on digital signal processing (DSP) including neural network, multimedia, and embedded workloads, and new projects in datacenter and scientific (supercomputing) kernels.

Research is accomplished with a multi-disciplinary view of algorithms, architectures, arithmetic, functional units, circuits, VLSI design, applications, and software tools of both programmable and special-purpose processors. We are one of very few university groups in the world that design and fabricate programmable (and configurable special-purpose) processor chips. Our research is grounded in achieving the aforementioned goals on widely-used applications measured in our laboratory on advanced deep-submicron CMOS fabricated chips which we have designed.

We believe we have designed the #1 and #2 highest clock rate fabricated processors and among the largest deep-submicron CMOS chips ever designed in a university.

Current Research & Sponsors



Downloadable Tools Developed in the VCL

VCL Laboratory Information

A Few Group Photos

People of the VCL

Professor Bevan Baas

Dr. Brent Bohnenstiehl

Graduate students
Derek Li
Ph.D. Student
  • Image compression
  • Hardware design
  • Architectures
Basheer Ammar
Ph.D. Student
  • Digital Systems
  • Architectures
  • Trigonometric functions
Yechengnuo Zhang
Ph.D. Student
  • Hardware accelerators
  • Hardware design
  • Architectures
Daniel Chevy
Ph.D. Student
  • Hardware design
  • Fast Fourier Transforms
  • Architectures
Michael Wang
MS Student
  • Discrete Cosine Transforms
  • Hardware design
  • Architectures
Sagar Sajeev
MS Student
  • FPGA design
  • Hardware design
  • Architectures
Dinesh Nagulapati
MS Student
  • Hardware design
  • Digital systems
  • Architectures
Open position
MS Student
  • Hardware design
  • Digital systems
  • Architectures
Undergraduate Researchers  
Catherine Kang
BS Student
  • Parallel Simulators
  • Programming environments
  • Platform development
Prof. Zhiyi Yu
Ph.D. ECE, Oct. 2007
Associate Professor
Sun Yat-Sen and Carnegie Mellon University

  • Network on chip
  • GALS clocking
  • AsAP 1.0 physical design
Prof. Tinoosh Mohsenin
Ph.D. ECE, Nov. 2010
Associate Professor
Johns Hopkins University

  • LDPC algorithms
  • LDPC architectures and processor design
  • Many-core processor arrays
Dr. Anh Tran
Ph.D. ECE, Aug. 2012
Lead Hardware R&D Engineer
Cavium Inc., San Jose

  • On-chip interconnects
  • Multi-core architectures
  • VLSI DSP implementation
Dr. Zhibin Xiao
Ph.D. ECE, Dec. 2012
Senior Hardware Engineer
Software-in-Silicon R&D Group
  • Memory system design
  • Video and multimedia applications
  • Processor shapes and topologies
Prof. Aaron Stillmaker
Ph.D. ECE, Dec. 2015
Assistant Professor
California State University, Fresno
  • Many-core architecture
  • Physical design
  • Parallel many-core sorting
Dr. Bin Liu
Ph.D. ECE, Sep. 2016
Software Engineer
Machine Learning Group
  • AES encryption
  • DVFS circuits and algorithms
  • Core scaling
Dr. Jon Pimentel
Ph.D. ECE, Aug. 2017
Silicon Architecture Engineer
Many Integrated Core Group
  • Floating-point architecture
  • SAR image processing
  • Sparse matrix multiplication
Dr. Brent Bohnenstiehl
Ph.D. ECE, March 2020
Postdoctoral Researcher
  • Processor architectures
  • VLSI Design
  • Software tool development
Dr. Shifu Wu
Ph.D. ECE, Sept. 2021
  • Image processing
  • Display Stream Compression
  • Algorithm design
Dr. Satyabrata Sarangi
Ph.D. ECE, September 2022
  • Huffman decoders
  • VLSI design
  • Hardware architecture
Dean Truong
MS ECE, May 2010
  • AsAP2 architecture and chip design
  • DVFS circuits and algorithms
  • Programming tools
Dr. Forough Mahmoudabadi
Research Scientist
Device Development Engineer
  • CMOS chip design
  • FD-SOI body bias circuits
  • Full-custom layout
Ryan Apperson
MS ECE, Sept. 2004
Senior Electrical Engineer
Physio-Control R&D

  • Asynchronous data interfacing circuits
  • SRAM design
  • Full-custom CMOS layout
Omar Sattari
MS ECE, Sept. 2004
Software Engineer
    Allied American University
  • Address generation and branching
  • Programming assembler, config
  • FFT algorithm mapping
Mike Lai
MS ECE, Sept. 2004
Design Engineer

  • High-speed pipelined signed multiplier
  • High-speed modular signed adder
  • Full-custom CMOS layout
Mike Meeuwsen
MS ECE, April 2005
Hardware Engineer
Intel, Digital Enterprise Group

  • 802.11a algorithm mapping
  • Architectural enhancements
  • Instruction set design
Toney Jacobson
MS ECE, July 2007
Patent Associate
Fenwick & West LLP

  • Fast Fourier Transform (FFT) architectures
  • Digital system design
  • High-speed FPGA design
Eric Work
MS ECE, Sept. 2007
Software Engineer
Soft Machines

  • Arbitrary task to 2D mesh mapping
  • Software tool flow
  • CAD tools
Wayne Cheng
MS ECE, January 2008
ASIC Design Engineer
  • Dynamic voltage supply circuits
  • Dynamic voltage and frequency circuits
  • Transistor-level power simulations
Gouri Landge
MS ECE, December 2009
Intel, Digital Home Group
  • Video motion estimation architectures
  • VLSI 65 nm motion estimation accelerator
  • Programmable video processing hardware
Stephen Le
MS ECE, March 2010
Component Design Engineer
Architecture Simulation
Intel, Visual Computing Group
  • Parallel H.264 application development
  • High-speed parallel simulator
  • Tool integration
Jeremy Webb
MS ECE, March 2011
  • High-speed board design
  • Many-core VLSI
  • System interfacing
Lucas Stillmaker
MS ECE, September 2011
Graphics Hardware Engineer
Intel, Visual and Parallel Computing Group (VPG)
Intel Architecture Group (IAG)
  • Parallel application development
  • Parallel database sorting algorithms
  • Digital system design
Trevin Murakami
MS ECE, December 2011
Product Engineer
NAND Solutions Group (NSG)
  • Many-core simulator
  • Processor architectures
  • Digital signal processing hardware
Houshmand Shirani Mehr
MS ECE, June 2012
Media encoder design, Component Design Engineer.
Intel, Visual and Parallel Computing Group (VPG HW)
Media Group
  • Digital signal processing hardware
  • Low Density Parity Check (LDPC) Decoders
  • LDPC Algorithms
Nima Mostafavi
MS ECE, June 2014
Hardware Engineer
Microelectronics Group
  • Hardware design
  • DSP applications
  • Software tools
Michael Braly
MS ECE, December 2015
Product Engineer
New Product Introduction
  • Motion estimation engines
  • Video compression
  • Processor architectures
Emmanuel Adeagbo
MS ECE, February 2017
Physical Design Engineer
Big Core, Platform Engineering Group (PEG)
  • Regular expression applications
  • Many-core tools
  • VLSI Design
Peiyao Shi
MS ECE, October 2018
Product Development Engineer
NAND Solutions Group (NSG)
  • Sparse matrix vector engines
  • Many-core linear algebra engines
  • System Design
Filipe Borges
MS ECE, September 2019
Silicon Engineering Group
  • DSP applications
  • Custom processor design
  • Application design
Christi Tain
MS ECE, September 2019
Hardware Validation Engineer
Storage Group
  • CMOS chip design
  • Place & route optimization
  • Processor architecture
Renjie Chen
MS ECE, September 2019
Moffett AI
  • Wireless architectures
  • DSP algorithms
  • Digital architectures
Arthur Hlaing
MS ECE, March 2020
  • LSTM Applications
  • 3D processor mapping
  • CAD tool development
Zhangfan Zhao
MS ECE, February 2021
  • Digital design
  • Matrix inversion
  • Hardware design
Sharmila Kulkarni
MS ECE, March 2021
  • Arithmetic coding
  • H.264 CABAC
  • Digital system design
Yikai Mao
MS ECE, September 2021
Ph.D. student, Keio University
  • YOLO neural network
  • Many-core application design
  • Convolutional neural networks
Haotian Wu
MS ECE, December 2021
RTL Design Engineer
  • Residual neural nets
  • Digital design
  • Neural net architectures
Tony (Wai Cheong) Tsoi
MS ECE, May 2022
  • Software-defined radio
  • Automated test design
  • RF interfaces
Christian Lum
MS ECE, June 2022
Northrop Grumman
Payload System Engineering
  • Digital System Design
  • Hardware Neural Networks
  • Radio Algorithms
Benjamin Moore
MS ECE, June 2022
R&D Engineer, FPGA/DSP
  • Software-defined radio
  • Radio algorithms
  • RF circuits
Ziyuan Dong
MS ECE, August 2022
Intel CG
Product Development Engineer
  • SqueezeNet Neural Net
  • Architectures
  • Hardware design
Aidan Callahan
MS ECE, November 2022
Product Development Engineer
  • Video compression architectures
  • H.264
  • Hardware design
Thomas Abbott
MS ECE, July 2023
  • Image compression
  • Parallel algorithms
  • Digital architectures
Santhosh Sammeta
MS ECE, September 2023
  • FPGA design
  • PCIe interfaces
  • Test strategies
Jin Cui
MS ECE, December 2023
  • SOI body-bias circuits
  • Processor circuit architectures
  • Intelligent optimization circuits
Yuxuan Huo
MS ECE, January 2024
  • Numerical algorithms
  • Transcendental functions
  • Arithmetic optimization
Undergraduate Researchers  

Henna Huang
BS ECE, June 2009
Ph.D. Student
  • Parallel H.264 application development
  • Multi-processor characterization
  • Tool development

Gary Chung
BS ECE, August 2009
Apple Computer
  • Embedded processor code development
  • File system design and implementation
  • Config design of 334-processor system

Brian Zimmer
BS ECE, June 2010
Ph.D. Student
UC Berkeley
  • MP3 decoder reference design
  • MP3 decoder implementation

Layne Miao
BS ECE, June 2011
Analog Design Engineer
Intel Corporation
  • AsAP2 board bring up
  • System characterization

Victoria Harvey
BS ECE, June 2012
Ph.D. Student
  • Many-core simulation
  • Application development
Jonathan Earl
BS ECE, June 2015
Maxim Integrated
  • Motion estimation
  • Video processing
  • Many-core application development
Dylan Finch
BS ECE, June 2017
Redpine Signals
  • MP3 parallelization
  • Parallel application development
  • Audio processing methods
Delvin Huynh
BS ECE, June 2018
  • Software-defined radios
  • Many-core radios
  • Laboratory SDR hardware
Sarvagya Singh
BS ECE, March 2018
Autonomous Driving Intern
Xpeng Motors
  • Many-core visualization
  • CAD tool development
  • Parallel application development
Yuanyuan Xiang
BS ECE, June 2018
MS Student
  • Many-core arithmetic
  • Floating-point algorithms
  • Fast division
Hangyu Meng
(Summer 2018)
Zhejiang University
  • Digital design
  • HW architectures
  • Hardware design
Ruochen Jiao
(Summer 2018)
Zhejiang University
  • Digital design
  • HW architectures
  • Hardware design
Ryan Atkins
  • DRAM interface design
  • FPGA development
  • Hardware design
Jiayu Wang
  • Software-defined radio
  • Digital design
  • Radio algorithms
Ryan Ma
  • Squeezenet architecture
  • Convolutional neural nets
  • FPGA design
  • William Au Yeung,   BS ECE, June 2005
  • Tomoko Tsuruta,   BS ECE, June 2005
  • Jason Cheung,   BS CS, June 2005
  • Leo Chan,   BS ECE, June 2006
  • Bassem Saad,   BS ECE, June 2006
  • Daniel Gurman,   BS ECE, June 2006
  • Sam Lee,   BS ECE, June 2006
  • Chi Chen,   BS ECE, June 2006
  • Kyle Piper,   BS ECE, June 2007

Current Research


In The News

Projects for Interested Graduate Students

Downloadable Tools Developed in the VCL

VCL Laboratory Information

Laboratory Resources

General Informative Web Pages

Some of the CAD and Other Tools We Use

Other Useful Links

Informative References

A few group pictures

[Some VCL alumni]
Alumni: Eric Work, Dr. Zhibin Xiao, Wayne Cheng, Bevan Baas, Mike Lai, Michael Braly at ECExpo, Santa Clara, Feb 26, 2020.

[Some VCL students]
Tim, Brent, Prof. Zhiyi Yu, Prof. Aaron Stillmaker, Shifu, Bevan, Satyabrata, Dr. Anh Tran, Prof. Tinoosh Mohsenin, Dr. Zhibin Xiao at ISSCC, Feb 18, 2019.

[Some VCL students]
Sharmila, Tim, Yushan, Felipe, Yuanyuan, Renjie, Bevan, Sarvagya, Shifu, Satyabrata, Jin, Mark at graduation ice-cream celebration; June 14, 2018.

[Some VCL students]
Yushan, Yuanyuan, Sharmila; June 14, 2018.

[Some VCL students]
Tim, Satyabrata, Jon, and Shifu at Jon's graduation ceremony; June 15, 2017.

[Some VCL students]
Shifu, Satyabrata, Emmanuel, Aaron, and Lucas at Aaron and Emmanuel's graduation ceremony; June 9, 2016.

[Some VCL students]
Brent, Aaron, Jon, and Emmanuel finishing up the KiloCore2 tapeout; March 1, 2015.

[Some VCL students]
Lucas, Aaron, Bevan, Zhibin, Jon, and Anh at Zhibin and Lucas' graduation ceremony; June 14, 2012.

[Some VCL students]
Aaron, Michael, Emmanuel, Jon, Anh, Samir, Zhibin, Brent, and Bin in the office-lab; April 4, 2012.

[Some VCL students]
Group dinner celebrating Jeremy, Lucas, and Trevin's graduations as well as Anh's best paper award and Bin's best paper nomination; January 25, 2012.

[Some VCL students]
Group lunch celebrating end of Spring quarter; June 10, 2009.

[Some VCL students]
Dean and Anh in office-lab; January 25, 2009.

[Some VCL students]
Dean, Zhibin and Paul in office-lab; March 27, 2008.

[Some VCL students]
Zhibin, Dean, Anh, Tinoosh, and Paul working on AsAP2 bringup; October 12, 2007.

[Some VCL students]
Tinoosh, Dean, and Zhibin working on AsAP2 bringup; October 11, 2007.

[Some VCL students]
Dean, Zhibin, Anh, Tinoosh, Paul, and Bevan at ECE Grad Student BBQ in Kemper courtyard; October 4, 2007.

[Some VCL students]
Toney, Wayne, Zhibin, Anh, Zhiyi, Tinoosh, Paul, Dean, and Bevan celebrating Toney's and Wayne's graduations at Woodstock's; August 29, 2007.

[Some VCL students]
Tinoosh, Dean, Christine, Wayne, and Zhiyi in Kemper 2211; November 8, 2006.

[Some VCL students]
Ryan, Omar, Mike M., Zhiyi, Mike L., and Bevan near the quad after lunch; August 26, 2004.

ECE Dept. | UC Davis

Last update: October 30, 2019
Keywords: many-core, multi-core, array processor, homogenous, heterogeneous, NoC, network on chip, interconnect, mesh, GALS, globally asynchronous locally synchronous, electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, ASIC, FPGA, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver, H.264 video compresssion encoding decoding, encoder decoder, codec, AES encryption decryption, networks on-chip, on-chip networks, routers, source-synchronous, interconnects, interconnection